Meeting Pearls 1/Meeting Pearls Vol 1 (1994).iso/installed_progs/text/faqs/lsi-cad-faq.part4

Internet Message Format | 1994-05-08 | 36.7 KB

Subject: comp.lsi.cad Frequently Asked Questions With Answers (Part 4/4) [LONG]
Newsgroups: comp.lsi,comp.lsi.cad,news.answers,comp.answers
From: [e-mail] (Michael Altarriba)
Date: Fri, 6 May 1994 22:12:02 GMT

Archive-name: lsi-cad-faq/part4


  The general steps for a university to begin using MagiCAD for digital
  GaAs gate array design include:
    1) Contact Mayo Foundation to acquire MagiCAD software
    2) Contact MOSIS to acquire general MOSIS information
       and Vitesse-specific technology information.

  Point Of Contact For Acquiring MagiCAD And MagiCAD Support:

          Thomas J. Smith
          Mayo Foundation
          Special Purpose Processor Development Group
          200 First St. S. W.
          Rochester, Minnesota 55905
          Telephone:  [phone]
          Telefax:    [phone]
          EMail:      [e-mail]

          Point Of Contact For Acquiring General MOSIS Information
                          And Vitesse-specific Technology Information:

          Sam Reynolds
          The MOSIS Service
          USC/ISI
          4676 Admiralty Way
          Marina del Rey, CA  90292-6695
          Telephone:  [phone] x172
          Telefax:    [phone]
          EMail:      [e-mail]

50: XSPICE, extended version of Spice

  (from Jeff Murray <[e-mail]>)

     I am one of the developers of XSPICE, and at the risk of being deluged
  with requests for specific information on the tools, I can volunteer to
  answer at least some questions. Currently there is no ftp site for infor-
  mation; if there were, this posting would likely be unnecessary. However,
  we are prohibited from posting even the User's Manual due to technology
  export restrictions.

     The following is a copy of the original press release on XSPICE.  If
  anyone would like additional clarification beyond this, or if some
  aspects of the release are unclear, we can certainly take this as an
  opportunity to remedy the situation. Please note that at the current time
  there are many dozens of individuals who have obtained a copy of the
  tools; if they have any comments or observations to make, I'm sure they
  would be most welcome to other members of the user community.

                          XSPICE Press Release

                            January 2, 1993

                   Georgia Tech Research Corporation

  XSPICE, introduced at the 1992 International Symposium on Circuits and
  Systems (ISCAS), is an extended and enhanced version of the popular SPICE
  analog circuit simulation program originally developed at the University
  of California at Berkeley. XSPICE was developed at the Georgia Tech
  Research Institute (GTRI) as a tool for simulating circuits and systems
  at multiple levels of abstraction. XSPICE permits a user to simulate ana-
  log, digital, and even non-electronic designs from the circuit level
  through the system level in a single simulator.  A special Code Modeling
  feature allows users to add new models directly into the simulator exe-
  cutable for maximum simulation speed and accuracy. Code models are writ-
  ten in the C programming language allowing arbitrarily complex behavior
  to be described. Code model development tools are provided to simplify
  the process of creating new models, compiling them, and linking them with
  the XSPICE core.

  XSPICE provides a rich set of predefined code models in addition to the
  standard discrete device models available in SPICE. The XSPICE code model
  library contains over 40 new functional blocks including summers, multi-
  pliers, integrators, magnetics models, limiters, S-domain transfer func-
  tions, digital gates, digital storage elements, and a generalized digital
  state-machine.

  Digital functions are simulated in XSPICE through an embedded event-
  driven algorithm added to the SPICE core. This algorithm is coordinated
  with the analog simulation algorithm to provide fast and accurate simula-
  tion of mixed-signal circuits and systems. The event-driven algorithm
  supports a new "User-Defined Node" capability allowing additional event-
  driven data types to be defined and used.  XSPICE comes with a 12-state
  digital data type as well as a user-defined node library that includes
  'real' and 'integer' types useful in simulating sampled-data systems such
  as Digital Signal Processing algorithms.

  XSPICE is currently available for UNIX workstations and is supplied in
  source code form allowing users to customize and extend the simulator and
  models to particular needs. To date, the simulator has been successfully
  compiled and used on HP Apollo and Sun workstations. The XSPICE simulator
  and User's Manual are available with a cost-free license arrangement from
  the Georgia Tech Research Corporation for a distribution charge of US
  $200 (including first class postage within the U.S.A.; an additional US
  $25 is required for overseas delivery by air). For further information,
  please contact the Office of Technology Licensing, Georgia Tech Research
  Corporation, Georgia Institute of Technology, 400 Tenth Street, Atlanta,
  GA 30332-0415, USA, or phone [phone] (voice) or [phone]
  (FAX). Internet users may send email to [e-mail] to obtain
  copies of the order form and license agreement (please include the word
  "license" in the subject header when mailing to this address).

51: MISIM, a model-independent circuit simulation tool

  (from Bardo Muller <[e-mail]>)

  University of Washington has recently released the updated MISIM simula-
  tor.  The new release (Sun version) is now available through ftp with
  anonymous login. The node address is 128.95.31.10. The release is under
  /pub/misim.SUN.2.3.a. If you have any question, please don't hesitate to
  contact us ([e-mail]). Or, you can contact Prof.
  Andrew Yang at 206-543-2932.

    Attention:
    ---------

  We are currently re-writing the whole MISIM system in C with broader
  design consideration. The noise and temperature simulation capability
  will be incorporated into our next release. It would have more flexible
  front end with better simulation performance.  The new version is
  expected sometime around the end of this summer.  Since the actual
  release no longer reflected the level of our technology, we removed it
  from our ftp directory.

                                         MISIM Development Team
                                         Department of Electrical Engineering
                                         University of Washington

                      MISIM 2.3A Release:  General Information
                     ------------------------------------------

  A) New capabilities:
     ----------------

  MISIM 2.3A is distinguishable from the previous release in that is now
  integrates a transistor-level mixed analog-digital simulator based on
  analytical digital macromodeling. The mixed-signal simulator is equipped
  with a front-end translator which accepts standard SPICE netlist syntax
  and converts it into MISIM mixed-mode syntax. Analytic macromodels for
  digital subcircuits are generated and loaded into MISIM core simulator
  automatically. Synchronized simulation is then performed for the digital
  subcircuits (processed by analytic solution) and the analog subcircuits
  (processed by proven analog simulation algorithms) with much accelerated
  speed and superior analog accuracy ( within 3-5 % of SPICE).

  The MISIM mixed-signal simulator supports all standard Berkeley MOS model
  (Level 1, 2, 3, BSIM 1, BSIM 2). User-defined MOS models of arbitrary
  complexity are also supported.

  Currently, the procedure of processing analytic digital macromodeling
  cannot be applied to bipolar devices (G-P model). Hence, all bipolar
  transistors will be simulated as "analog" components.

  MISIM's X-window graphic environment, WISE, has been upgraded to support
  the mixed-signal simulation capabilities.

  B) Model Improvements:
     ------------------

  MISIM 2.3A now supports improved SPICE models (MOS, Diode, BJT). Many of
  the model discontinuities have been resolved leading to more reliable
  simulation. The MOS Level 2 and Level 3 models have also been upgraded to
  an improved charge-conserved models.  The standard SPICE diode model has
  been enhanced to a non-quasi-static model capable of simulating accu-
  rately the diode recovery effect.

  These improved SPICE models are released as linked models. Users are not
  recommeded to unload these improved models.

  C) A New Parser:
     ------------

  MISIM 2.3A incorporates a new netlist parser which supports two different
  modes:

  1) Standard SPICE netlist syntax - default mode.  2) Enhanced SPICE net-
  list syntax - MISIM mode.

  This new capability is designed to make MISIM completely spice-
  compatible. In addition, the new parser now handles symbolic names and
  expressions.

  D) Updated Documentations:
     ----------------------

  An updated MISIM User's guide is available in postcript form. On-line
  documentations is also provided.

  E) Future Release (MISIM 3.0):
     --------------------------

  1) The next release will include a new C-version analog simulator which
  has been benchmarked to be a factor of 2 to 3 times faster than the
  current fortran version.

  2) The mixed-signal simulator will be enhanced to improve digital cover-
  age rate (percentage of a mixed A/D circuit which can be processed by the
  analytic digital macromodel) for better simulation performance.

52: Nelsis Cad Framework

  (from their 'README' file)

  Release 4.3 is the latest version of the Nelsis IC Design System.  It
  contains  a CAD framework that puts a substantial added-value under the
  fingertips of the designer  by  organizing  the  design information  and
  keeping  track  of  the  design  evolution.  It permits integration of
  tools of  different  origin  and  achieves run-time  efficiency.   The
  framework  is  based  on intelligent management of meta data on top of
  the actual design descriptions; it administers high level information
  about the design activities and the structure and status of the design,
  rather than operating at the level of the detailed design descriptions.

  The  framework  services,  such  as  flow   management,   version manage-
  ment,  concurrency  control and state management, have been implemented
  on top of  the  meta  data  management  module.   The framework  controls
  access to the design objects and administers meta data by performing
  OTO-D queries.  Tools operate on  top  of the framework via the Data
  Management Interface, obtaining access to the design data according to a
  nested transaction schema.

  The Nelsis CAD Framework is available, together with a set of design
  tools for demonstration purposes, through anonymous ftp from
  dutente.et.tudelft.nl:pub/nelsis .

53: APLAC, a system-level simulator and IEEE-488 measurement tool

  (from Sakari Aaltonen <[e-mail]>)

          -----------------------------------------
                         APLAC 6.1
          -----------------------------------------

  General information

  APLAC, a program for circuit simulation and analysis, is a joint develop-
  ment of the Circuit Theory Lab of Helsinki University of Technology and
  Nokia Corporation's Research Center. The main analysis modes are DC, AC,
  noise, transient, oscillator, and (multitone harmonic) steady state.
  APLAC can also be used for measurements with IEEE-488 apparatus.  APLAC's
  transient analysis uses convolution for correct treatment of components
  with frequency-dependent characteristics. Monte Carlo analysis is avail-
  able in all basic analysis modes, as is sensitivity analysis in DC and AC
  modes. N-port Z, Y, and S parameters, as well as two-port H parameters,
  can be used in AC analysis. APLAC also includes a versatile collection of
  system level blocks for the simulation and design of analog and digital
  communication systems.

  Component models

  Too many to be listed here. In addition to familiar Spice models, a great
  number of microwave components (microstrip/stripline) are included. Sys-
  tem models include formula-based and discrete-time models useful in RF
  design. The model parameters of the components may have any functional
  dependency on frequency, time, temperature, or any other parameter. Users
  can create new components by defining their - possibly nonlinear - static
  and dynamic characteristics in APLAC's interpreter-type language. Spice-
  syntax models can be imported.

  Input

  APLAC reads its input - the nodes, branches, and model parameters of the
  components - from a text file. Model libraries can be created and
  included. Expressions are written in a program-like manner; user func-
  tions may be defined. Conditional and looping control structures are sup-
  ported.

  Output

  The output results from one or several sweeps of any user-defined func-
  tion of the circuit parameters, time, frequency, or temperature. The
  results may be printed or plotted in rectangular or polar coordinates, or
  on the Smith chart. Graphics output can be directed to an HPGL- or CSDF-
  type file, or to a graphics file for later viewing.

  Optimization

  APLAC includes several optimization methods: gradient, conjugate gra-
  dient, minmax, random, simulated annealing, tuning (manual optimization)
  and gravity center (design centering). Any parameter in a design problem
  can be used as a variable and any user-defined function may act as an
  objective.

  Machine environment

  Unix: X11;  PC: MS-Windows (math coprocessor required).

          Contact information
          -------------------
          Martti Valtonen                         Heikki Rekonen
          Helsinki University of Technology       Nokia Research Center
          Circuit Theory Laboratory               Hardware Design Technology
          Otakaari 5A, SF-02150 Espoo, FINLAND    P.O.Box 156, SF-02101 Espoo,
                                                  FINLAND
          Fax:  [phone]                      Tel:  [phone]
          e-mail:[e-mail]              Fax:  [phone]

  Free (university version) binaries for HP9000/700, Sun4, and PC machines
  are available via FTP from nic.funet.fi:pub/cae/aplac . Help files, PS
  manuals, and collections of APLAC examples are in the same directory.

54: SLS, a switch-level simulator

  (from comp.lsi.cad)

  DELFT UNIVERSITY OFFERS UNIQUE SWITCH-LEVEL SIMULATOR

  SLS is a switch-level simulator that can be used to simulate the logic
  and timing behavior of large digital circuits that are described at the
  (mixed) MOS transistor, gate and functional level.  It has fast and accu-
  rate algorithms to predict the timing behavior of MOS circuits containing
  > 100,000 transistors.  MOS transistor-level circuit descriptions are
  easily mixed with gate-level and functional-level circuit descriptions,
  where the behavior of the latter are described in the C programming
  language.  There is an X-window based user-interface to graphically edit
  the input signals and to inspect the simulation output signals. The same
  interface is used to alternatively simulate the circuit with the well-
  known circuit simulator SPICE.  SLS has already been used by many people
  at many different sites, and numerous chips have been designed with it.
  SLS is now made available world-wide to serve as a useful design and
  verification tool to the international design community.  Apart from
  being used as a stand-alone tool, SLS can also be used as a part of the
  popular design system for Sea-Of-Gates circuits OCEAN, or it can be con-
  nected to the advanced Nelsis CAD framework.

  The SLS simulator has three different simulation levels:

  1. Purely logic simulation based on abstract transistor strengths:
     This level more or less behaves similar to the original switch-level
     model as proposed by R.E. Bryant.  It computes logic states by
     only considering node states and transistor types.

  2. Logic simulation based on exact transistor dimensions and node
     capacitances: This level uses resistance division and capacitance
     division algorithms to compute logic states. It finds correct logic
     states in much more situations than conventional switch-level
     simulators, e.g. when a resistance division occurs between a saturated
     transistor and a non-saturated transistor.

  3. Logic and timing simulation based on transistor and node parameters:
     RC time constant evaluations are used to approximate real voltages by
     PIECEWISE-LINEAR VOLTAGE WAVEFORMS. This not only provides delay times
     for the circuit, but is also delivers an accurate representation for
     transient effects like spikes and races.

  Apart from electrical network elements like MOS transistors, resistors
  and capacitors, an SLS network may contain (i) gate primitives like
  inverters, nands, nors, etc. and (ii) user-defined function blocks like
  roms, shiftregisters, multipliers.  The behavior of function blocks is
  described by the user in the C programming language: it is specified by
  the user how the values of the output terminals and the state variables
  are computed from the values of the input terminals and the state vari-
  ables.

  For more information about SLS, see,

    "Switch-level timing simulation," P.M. Dewilde, A.J. van Genderen,
    A.C. de Graaf, Proc. ICCAD 85 Conf., Santa Clara, Nov. 1985,
    pp. 182-184

    "SLS: An Efficient Switch-Level Timing Simulator Using Min-Max Voltage
    waveforms," A.J. van Genderen, Proc. VLSI 89 Conf., Munich, Aug. 1989,
    pp. 79-88.

    "SLS: Switch-Level Simulator User's Manual," A.C. de Graaf, A.J. van
    Genderen, Delft University of Technology (available for ftp at the
    address below).

  Availability:

  SLS is written in C and runs under UNIX and X-windows.  It runs, among
  other things, on Sun SPARC stations, HP 9000 series 700/800 machines, and
  PCs running Linux.  The program is available for free under the terms of
  the GNU General Public License.  It can be retrieved via anonymous ftp
  from dutentb.et.tudelft.nl:pub/sls .

  It is also possible to obtain SLS as a part of the OCEAN system for the
  design of Sea-Of-Gates circuits.  This system can be obtained from on
  donau.et.tudelft.nl:pub/ocean .  The OCEAN system among other things con-
  tains a layout-to-circuit extractor that can extract large layouts and
  that stores the result directly in the database that is read by SLS.
  Furthermore, SLS is available as a tool in the Nelsis CAD framework from
  the directory pub/nelsis on dutente.et.tudelft.nl.  The latest version of
  SLS can always be found on dutentb.et.tudelft.nl .

  For questions, remarks and bug reports, contact

            Arjan van Genderen
            Delft University of Technology
            Department of Electrical Engineering
            Mekelweg 4                          phone: [phone]
            2628 CD  Delft                      fax: [phone]
            The Netherlands                     email: [e-mail]

  55: OCEAN, a sea-of-gates design system

  (from Patrick Groeneveld <[e-mail]>)

          About OCEAN: the sea-of-gates design system
          -------------------------------------------

  OCEAN is a comprehensive chip design package which was developed at Delft
  University of Technology, the Netherlands. It includes a full set of
  powerful tools for the synthesis and verification of semi-custom sea-of-
  gates and gate-array chips.  OCEAN covers the back-end of the design tra-
  jectory: from circuit level, down to layout and a working chip. In a nut-
  shell, OCEAN has the following features:

          + Available for free, including all source code.
          + Short learning curve making it suitable for student design courses.
          + Hierarchical (full-custom-like) layout style on sea-of-gates.
          + Powerful tools for placement, routing, simulation and extraction.
          + Any combination of automatic and interactive manual layout.
          + OCEAN can handle even the largest designs.
          + Running on popular HP, Sun and 386/486 PC machines, easy
            installation.
          + Includes three sea-of-gates images with libraries and a
            200,000 transistor sea-of-gates chip.
          + Can be easily adapted to arbitrary images with any number of layers.
          + Interface programs for other tools and systems (SIS, cadence, etc.)
          + Robust and 'combat-proven', used by hundreds of people.

   How to retrieve OCEAN and additional documentation?
   ---------------------------------------------------

  The entire OCEAN system is available for free via anonymous ftp, gopher
  or on tape. A powerful installation script is included, so you can get
  started very quickly without hacking up the code. You can retrieve OCEAN
  and additional documentation via:

          anonymous ftp: donau.et.tudelft.nl:pub/ocean
          gopher:        olt.et.tudelft.nl (port 70) or use the path
                         World --> Europe --> Netherlands -->
                         Delft University of Technology Electronic Engineering
                         --> Research activities -->
                         The OCEAN sea-of-gates Design System

  We advise to retrieve first the documents with the user manual. (The file
  'ocean_docs.tar.gz').  If you have any questions, remarks or problems,
  just contact us:

          Patrick Groeneveld or Paul Stravers
          Electronic Engineering Group, Electrical Engineering Faculty
          Delft University of Technology
          Mekelweg 4, 2628 CD   Delft  The Netherlands
          Phone: [phone]  Fax: [phone]
          Email: [e-mail]

56: ALLIANCE, a CAD package and simulator for teaching digital VLSI design

  (from Gilles-Eric DESCAMPS <[e-mail]>)

          ******************************************************
          *   ANNOUNCEMENT OF ALLIANCE RELEASE 2.0   17 Feb 94 *
          ******************************************************

          The release 2.0 of the public domain ALLIANCE VLSI/CAD system  is
          now available at:

          ftp.ibp.fr:ibp/softs/masi/alliance      [132.227.60.2]
          cao-vlsi.ibp.fr:pub/alliance            [132.227.60.20]

  CONTENT

  ALLIANCE is a complete set of CAD tools  and  portable  libraries for
  research and education in digital VLSI design.  The ALLIANCE CAD  system
  has been developed at the MASI laboratory (Universite Pierre et Marie
  Curie, Paris France). It includes a VHDL compiler and simulator, logic
  synthesis tools, automatic place and  route, DRC,  extractor,  functional
  abstraction  and formal proof tools etc...  All the ALLIANCE cell
  libraries  use  a  symbolic  layout approach in  order  to provide pro-
  cess independence: Cmos process from 1.6 micron to 0.8 micron have been
  successfully targetted.

  Several new  tools and portable cell libraries have been introdu- ced
  into release 2.0:

          * Six parameterized portable CMOS generators:
            - RAGE static RAM generator
            - GROG high speed ROM generator
            - RSA  fast adder generator
            - BSG  barrel-shifter generator
            - AMG  pipelined multiplier generator
            - RFG  multi-ports register file generator

          * A data-path compiler for high performance and high density cir-
            cuits (including a dedicated portable standard cell library)

          * A Finite State Machine Synthesiser  SYF,  the  logic  synthesis
            tool  LOGIC  and  the  net-list  optimizer  NETOPTIM  allow the
            implementation of high complexity  controllers from VHDL input.

          * A procedural layout debugger GENVIEW allows new  portable  gen-
            erators  or  custom blocks to be developed easily.  A new symb-
            olic layout editor GRAAL has a MOTIF interface.

  INSTALLATION

  ALLIANCE is totally free, under the terms of the GNU General Pub- lic
  License.  It includes C source files and on-line English do- cumentation
  (UNIX man)

  1) A hierarchical makefile allows each ALLIANCE tool to  be  com-
     piled and  installed separately.  The disk  space  required to
     compile  and  install  the full  ALLIANCE package is about 150
     megs.

  2) The release 2.0 has been successfully compiled with K&R cc and
     GNU gcc compilers. The full alliance package can  now  run  on
     SPARC, LINUX and DEC architectures.

  TUTORIALS

  The release ALLIANCE 2.0 contains three separate tutorials:

  1) ADDACCU
     The  design  of a  very simple chip (adder/accumulator) to get
     started with the ALLIANCE tools (about 500 transistors).

  2) AMD2901
     The design of the 4 bits AMD2901 processor, from the VHDL spe-
     cification  to the  GDSII  layout, using the ALLIANCE portable
     standard cell library (about 3000 transistors).

  3) DLX
     The  design of the 32 bits DLX microprocessor (HENNESSY & PAT-
     TERSON) from the VHDL specification to the GDSII layout, using
     the  ALLIANCE  data-path  compiler  and  logic synthesis tools
     (about 30000 transistors).

57: ceBox EDIF Viewer

  <from comp.archives>

  A free demo version of the ceBox EDIF Viewer is now available on the
  ftp-server:

          ftp.Germany.EU.net:shop/concept-engineering/EDIF        [192.76.144.75]

  you find the following files:

          README.german                   (  2k  ASCII text)
          README.english                  (  2k  ASCII text)
          demo.edif.Z                     ( 10k  EDIF file)
          edif_viewer_demo.Z              (808k  SPARC executable)
          tutorial-demo-viewer.ps.Z       ( 31k  PostScript document)

  The  *ceBox EDIF Viewer*  displays schematic pages and symbols of any
  EDIF 200 (level 0) file. It is an easy-to-use tool to analyse EDIF
  schematic files.

  The  *ceBox EDIF Kit*  is a programming library to bundle C++ user func-
  tions to the Viewer and to build standalone EDIF processors.  The Kit's
  in-core data base allows to access/modify all EDIF data.

  For more information, please contact:

          Concept Engineering
          Burkheimer Str. 10
          D-79111 Freiburg
          Germany

          Tel: ..[phone]
          Fax: ..[phone]
          email: [e-mail]

58: Analog CMOS VLSI Design Educational Resource Kit

  (from MUG)

  UMass Dartmouth is pleased to announce the release of Version 1 of the
  Analog CMOS VLSI Design Educational Resource Kit.  Version 1 of the
  Resource Kit may be obtained via anonymous ftp at the site

          micron.ece.umassd.edu

  The release includes the following files and information:

  The CIF file for a 2 micron Mosis Tinychip using p-well technology; and
  manuals containing five tutorials based on the chip set.

  These circuits were used in an undergraduate course on analog VLSI design
  during the spring semester at the University of Massachusetts Dartmouth.
  They are also being currently used in a graduate level course in analog
  VLSI design.  The students in the undergraduate course had a single
  introductory digital VLSI design course as background, and were familiar
  with MAGIC, SPICE and CAzM, a SPICE-like circuit simulator.

  If you have any comments, corrections or suggestions regarding the
  release, or ideas for other circuits that you have found useful in your
  classes and that could be incorporated in later releases, please feel
  free to contact me.  Good luck!

          Robert H. Caverly, Ph.D.
          ECE Department
          University of Massachusetts Dartmouth
          N. Dartmouth, MA  02747
          [e-mail]
          [phone]

59: TDX Fault Simulation and Test Generation Software

  (from Dan Holt <[e-mail]>)

  TDX Fault Simulation and Test Generation Software

  Free demo/student copies of Attest Software's fault simulation, Iddq,
  DFT, and automatic test pattern generation tools are available by
  anonymous ftp.

  This software is fully functional on any circuit with less than 1000
  gate-level primitives. It is also fully functional on the GL85 micropro-
  cessor circuit (about 3000 primitives) which is included with the suite
  of tools. General-use licenses can be provided free to accredited univer-
  sities for non-commercial, educational purposes.

  The software is built around a high-performance concurrent fault simula-
  tor that is accurate on a wide-range of state and timing sensitive cir-
  cuits. It supports synchronous and asynchronous designs containing logic
  gates, MOS transistors, tri-state buffers, flip-flops, single/multi-port
  RAMs, complex bus resolution functions, and Verilog User Defined Primi-
  tives (UDPs).  The software also supports the detailed pin timing and
  strobing features found on "tester-per-pin" automatic test equipment. The
  software supports Verilog and VHDL netlists.

  The GL85 microprocessor, which is a clone of the once-popular 8085
  microprocessor, is a fully functional model for which three views are
  provided: behavioral, RTL, and gate level.  Using this clone, a tutorial
  shows the user how to achieve improved controllability and/or observabil-
  ity for his or her circuit, resulting in improved fault coverage, some-
  times with very little additional time or effort expended in the design
  cycle. The tutorial was written by Dr. Alex Miczo.

  The software is available by ftp from netcom.netcom.com:pub/attest.  The
  README contains installation instructions, and identifies the location of
  the GL85 models and the postscript tutorial.

  For more information, please contact:

              Attest Software Inc.
              4677 Old Ironsides Drive, Suite 100
              Santa Clara CA 95054 USA

              [phone]  voice
              [phone]  fax

              [e-mail]

60: Nascent Technologies CDROM - magic and spice releases for Linux

  The Linux from Nascent CDROM, Version 1.0, is only $39.95 plus shipping
  and handling, and comes with an 30-day unconditional money-back guaran-
  tee.  If you aren't completely satisfied, return the package with your
  receipt within 30 days and the purchase price, excluding shipping and
  handling, will be refunded to you.

  In addition, Nascent offers the Linux from Nascent Plus package for only
  $89.95, which includeds six months of email support and a 30% discount
  off a future release of the CDROM with your CDROM purchase.

          Nascent Technology
          811 Haverhill Drive
          Sunnyvale CA 94087 USA
          Tel: [phone]
          Fax: [phone]
          Email: [e-mail]

  Linux is a freely distributable Unix(R) compatible operating system for
  the IBM(R) 386/486 PC and compatibles written by Linus Torvalds from the
  University of Helsinki, Finland.  It was developed by a unique world-wide
  collaboration of programmers over the internet, and is covered by the GNU
  General Public License.  Linux is a modern, high performance network
  operating system, much like ones used for years on engineering and pro-
  fessional workstations.

  The Linux from Nascent CDROM is an entirely new distribution of the Linux
  operating system, and includes over 400 mbytes of source code, binaries,
  and documentation for Linux and applications.  The Linux from Nascent
  distribution features:

          * 52 page User Guide
          * automated root, swap, and package installation from CDROM
          * simple user account and network administration scripts
          * Linux 0.99.14 plus net-2 networking
          * extensive online documentation and manuals
          * network printer support
          * X Window System(TM)
          * OpenLook(TM) 3d window manager
          * SCSI disk and tape support
          * TeX(TM) and ghostscript word processor and viewer
          * Ingres database management
          * GNU C compiler and utilities
          * GNU emacs, vi clone text editors
          * sound and graphics support
          * Over 100 high resolution images translated from Kodak PhotoCD(TM)
          * magic and spice electronic design tools
          * GNU Chess, Shogi, pooltable, xpilot, flight simulator, ...

61: Time Crafter 1.0, a timing diagram documentation tool

  (from Rick Burgett <[e-mail]>)

  I have uploaded to the SimTel Software Repository (available by anonymous
  ftp from the primary mirror site
  OAK.Oakland.Edu:pub/msdos/electric/timecrft.zip and its mirrors):
  timecrft.zip    WIN3: Electronic ckt timing diagram generator

  Time Crafter Version 1.0 is a timing diagram documentation tool.  A tim-
  ing diagram is used by electrical engineers and technicians to document
  the way a circuit or system operates or should operate.  This type of
  documentation is crucial to good design and debugging but up to now one
  could only use paper and pencil (with a good eraser) or an expensive CAD
  package costing $1000 or more to produce these diagrams on a PC.  Time
  Crafter has features that make it easy to document and update a circuit
  design of any complexity.

  Time Crafter is Microsoft Windows based to provide a simple yet powerful
  user interface which is device independent.

  Special requirements: Windows 3.x

  62: ACS, a general purpose mixed analog and digital circuit simulator

  (from comp.lsi.cad)

  A new version of ACS (Al's Circuit Simulator) has been posted to
  alt.sources.  It is also available by ftp from cs.rit.edu:pub/acs or
  ee.rochester.edu:pub/acs .   If you don't have net access you can get it
  by dial-up from (USA) 716-272-1645.

  ACS is a general purpose mixed analog and digital circuit simulator.  It
  performs nonlinear dc and transient analyses, fourier analysis, and ac
  analysis linearized at an operating point.  At this point the analog is
  stronger than the digital.  (In fact, the digital part is rather weak.)
  It is fully interactive and command driven.  It can also be run in batch
  mode or as a server.  The output is produced as it simulates.  Spice com-
  patible models for the MOSFET (level 1 and 2) and diode are included in
  this release.

  This version (0.13) includes several improvements including real Fourier
  analysis and better time step control based on truncation error.  There
  are other minor improvements.

  Since it is fully interactive, it is possible to make changes and re-
  simulate quickly.  The interactive design makes it well suited to the
  typical iterative design process used it optimizing a circuit design.  It
  is also well suited to undergraduate teaching where Spice in batch mode
  can be quite intimidating.  This version, while still officially in beta
  test, should be stable enough for basic undergraduate teaching and
  courses in MOS design, but not for bipolar design.

  In batch mode it is mostly Spice compatible, so it is often possible to
  use the same file for both ACS and Spice.

  The analog simulation is based on traditional nodal analysis with itera-
  tion by Newton's method and LU decomposition.  An event queue and incre-
  mental matrix update speed up the solution for large circuits.

  It also has digital devices for true mixed mode simulation.  The digital
  devices may be implemented as either analog subcircuits or as true digi-
  tal models.  The simulator will automatically determine which to use.
  Networks of digital devices are simulated as digital, with no conversions
  to analog between gates.  This results in digital circuits being simu-
  lated faster than on a typical analog simulator, even with behavioral
  models.  The digital mode is experimental and needs work.  There will be
  substantial improvements in future releases.

  The source and documentation can be obtained by anonymous ftp from
  ee.rochester.edu:pub/acs or cs.rit.edu:pub/acs .  It can also be obtained

  by dial-up (USA) 716-272-1645 in /pub/acs.  It may be distributed under
  the terms of the GNU general public license.  The dial-up also has some
  test circuits, pre-compiled executables for Next, Sun4, MSDOS and possi-
  bly others, and documentation in dvi and postscript.

63: LOG/iC, a logic synthesis package for PLDs

  (from Ralph Remme <[e-mail]>)

          LOG/iC EVAL
          - - ISDATA GmbH Karlsruhe, Germany / ISDATA Inc. Oakland CA
          - - FSM and logic synthesis for programmable logic devices
          - - Several output formats: JEDEC, POF, HEX, EDIF, XNF, Open-PLA,
              PALASM, ...
          - - PLD data base as an electronic reference
          - - PC Windows
          - - free version of LOG/iC PLUS for educational and research use only
          - - anonymous ftp: gate.fzi.de:pub/ISDATA (141.21.4.3)
          - - email: [e-mail]

          ISDATA GmbH                     ISDATA Inc.
          Daimlerstrasse 51               P.O. Box 19278
          D-76185 KARLSRUHE               Oakland, CA 94619
          GERMANY                         U.S.A.
          Phone:[phone]        Phone: (++1) 510 5318553
          FAX:   [phone]       Fax:   (++1) 510 5318417
          Mr. Peter Bauer                 Mr. Paul Hoy